8259 PIC Microcontroller

8259 PIC Microcontroller

Intel 8259 is a Programmable Interrupt Controller (PIC). There are 5 hardware interrupts and 2 hardware interrupts in Intel 8085 and Intel 8086 microprocessors respectively. But by connecting Intel 8259 with these microprocessors, we can increase their interrupt handling capability. Intel 8259 combines the multi-interrupt input sources into a single interrupt output. Interfacing of a single PIC provides 8 interrupt inputs from IR0-IR7. For example, the Interfacing of 8085 and 8259 increases the interrupt handling capability of 8085 microprocessors from 5 to 8 interrupt levels. 

Features of Intel 8259 PIC are as follows: 

1.      Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessors.

2.      It can be programmed either in the level triggered or in the edge-triggered interrupt level.

3.      We can mask individual bits of the interrupt request register.

4.      We can increase interrupt handling capability up to 64 interrupt levels by cascading further 8259 PICs.

5.      Clock cycle is not required.


Pin Diagram of 8259 –  We can see through the above diagram that there is a total of 28 pins in Intel 8259 PIC where Vcc: 5V Power supply and Gnd: ground. Other pins used are explained below. 



Block Diagram of 8259 PIC microprocessor –


 

The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write Logic, Cascade Buffer Comparator, Control Logic, Priority Resolver, and 3 registers- ISR, IRR, and IMR.

  1. Data bus buffer – This Block is used as a mediator between 8259 and 8085/8086 microprocessor by acting as a buffer. It takes the control word from the 8085 (let's say) microprocessor and transfers it to the control logic of the 8259 microprocessor. After the selection of Interrupt by 8259 microprocessor (based on the priority of the interrupt), it transfers the opcode of the selected Interrupt and address of the Interrupt service subroutine to the other connected microprocessor. The data bus buffer consists of 8 bits represented as D0-D7 in the block diagram. Thus, this shows that a maximum of 8 bits of data can be transferred at a time.
  2. Read/Write logic – This block works only when the value of pin CS is low (as this pin is actively low). This block is responsible for the flow of data depending upon the inputs of RD and WR. These two pins are active low pins used for read and write operations.
  3. Control logic – It is the center of the PIC and controls the functioning of every block. It has pin INTR which is connected with other microprocessors for taking interrupt requests and pin INT for giving the output. If 8259 is enabled, and the other microprocessor's Interrupt flag is high then this causes the value of the output INT pin high and in this way 8259 responds to the request made by other microprocessors.
  4. Interrupt request register (IRR) – It stores all the interrupt levels which are requesting Interrupt services.
  5. Interrupt service register (ISR) – It stores the interrupt level which is currently being executed.
  6. Interrupt mask register (IMR) – It stores the interrupt level which has to be masked by storing the masking bits of the interrupt level.
  7. Priority resolver – It examines all three registers and sets the priority of interrupts and according to the priority of the interrupts, the interrupt with the highest priority is set in the ISR register. Also, it reset the interrupt level which is already been serviced in IRR.
  8. Cascade buffer – To increase the Interrupt handling capability, we can further cascade more pins by using a cascade buffer. So, during the increment of interrupt capability, CSA lines are used to control multiple interrupt structures.

SP/EN (Slave program/Enable buffer) pin when set to high, works in master mode else in slave mode. In Non-Buffered mode, SP/EN pin is used to specify whether 8259 works as master or slave and in Buffered mode, SP/EN pin is used as an output to enable the data bus.


Notes:-

  

Comments

Post a Comment

Popular posts from this blog

Assignment Questions (Subject:- Microprocessor and Microcontroller)

  Microprocessor and Microcontroller Assignment Questions Instructions: ·          Solve any 8 questions in each section. ·          Make appropriate assumptions wherever necessary. Unit 1 1.       What is microprocessor? 2.       What is the difference between the microprocessor and microcontroller? 3.       Explain the register organization of 8086 4.       How many data lines and address lines are available in 8086? 5.       Explain briefly about the internal hardware architecture of 8086 microprocessor with a neat diagram 6.       What is the maximum memory size that can be addressed by 8086? 7.       Calculate the physical address for fetching the next instruction to be executed, in 8086? 8.  ...
Read more

Architecture of 8086

Image
A   Microprocessor   is an Integrated Circuit with all the functions of a CPU. However, it cannot be used stand-alone since unlike a microcontroller it   has no memory or peripherals .  8086 does not have RAM or ROM inside it. However, it has  internal registers  for storing intermediate and final results and interfaces with memory located outside it through the System Bus.  In the case of 8086, it is a 16-bit  Integer processor  in a 40-pin, Dual Inline Packaged IC.  The size of the internal registers(present within the chip) indicates how much information the processor can operate on at a time ( in this case 16-bit registers ) and how it moves data around internally within the chip, sometimes also referred to as the internal data bus.  8086 provides the programmer with 14 internal registers, each of 16 bits or 2 bytes wide.  The main advantage of the 8086 microprocessor is that it supports Pipelining. 8086 Architecture M...
Read more

Microprocessor - 8257 DMA Controller

Image
DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest rate. It allows the device to transfer the data directly to/from memory without any interference of the CPU. Using a DMA controller, the device requests the CPU to hold its data, address and control bus, so the device is free to transfer data directly to/from the memory. The DMA data transfer is initiated only after receiving HLDA signal from the CPU. How DMA Operations are Performed? Following is the sequence of operations performed by a DMA − Initially, when any device has to send data between the device and the memory, the device has to send DMA request (DRQ) to DMA controller. The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert the HLDA. Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU leaves the control over bus and acknowledges the HOLD request through HLDA signal. Now the CPU is in HOLD state and the DMA control...
Read more