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Programmable Interval Timer 8254

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8254 is a device designed to solve the timing control problems in a microprocessor. It has 3 independent counters, each capable of handling clock inputs up to 10 MHz, and size of each counter is 16 bit. It operates in +5V regulated power supply and has 24 pin signals. All modes are software programmable. The 8254 is an advanced version of 8253 which did not offered the feature of read back command.  8254 Architecture/ B asic Block Diagram The architecture/  basic block diagram  of 8254 looks as follows − 8254 Pin Description Here is the pin diagram of 8254 − Pin Diagram 8254 In the above figure, there are three counters, a data bus buffer, Read/Write control logic, and a control register. Each counter has two input signals - CLOCK & GATE, and one output signal - OUT. Data Bus Buffer It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the system data bus. It has three basic functions − Programming the modes of 8253/54. Loading the count regis
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Microprocessors and Microcontrollers BE(EE/EEE) 5th Upcoming topics

Unit-I: Microprocessor 8086Introduction to 16-bit 8086 microprocessors, architecture of 8086, Pin Configuration, interrupts, minimum mode and maximum mode, timing diagram, Memory interfacing. Comparative study of Salient features of 8086, 80286 and 80386. Unit-II: Microprocessor 8086 programming Instruction set of 8086, Addressing mode, Assembler directives & operations, assembly and machine language programming, subroutine call and returns, Concept of stack, Stack structure of 8086, timings and delays Unit-III: Input-Output interfacing: Memory Mapped I/O and Peripherals I/O. PPI 8255 Architecture and modes of operation, interfacing to 16-bit microprocessor and programming, DMA controller (8257) Architecture, Programmable interval timer 8254, USART 8251, 8-bit ADC/DAC interfacing and programming. Unit-IV: Microcontroller 8051Intel family of 8 bit microcontrollers, Architecture of 8051, Pin description, I/O configuration, interrupts; Interrupt structure and interrupt priorities,
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Microprocessors and Microcontrollers BE (EE/EEE) 5th sem

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Microprocessors and Microcontrollers ( 5th Semester Syllabus):-Upcoming topics

Unit-I Architecture of 8086 Microprocessor: -  BIU and EU, register organization, pin diagram, memory organization, clock generator 8284, buffers and latches, 8288 bus controller, maximum and minimum mode. Unit-II Assembly Language Programming of 8086:-  Instruction formats, addressing modes, instruction set, assembly language programming. ALP tools- editor, assembler, linker, locator, debugger, emulator. 8086-based multiprocessor systems:-  Interconnection topologies, coprocessors 8087 NDP. I/O processors 8089 IOP, bus arbitration and control, lightly and tightly coupled systems. Unit-III Peripheral devices and their interfacing:-  Memory interfacing. Programmable input/output ports 8255. Programmable interval timer 8253, keyboard display controller 8279, CRT controller 8275. Programmable communication interface 8251 USART Unit IV Interrupts of 8086:-  Interrupts and interrupt service routine, interrupt cycle, maskable and non-maskable interrupts, interrupt programming
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8255A - Programmable Peripheral Interface

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8255A - Programmable Peripheral Interface The 8255A is a general-purpose programmable I/O device designed to transfer the data from I/O to interrupt I/O under certain conditions as required. It can be used with almost any microprocessor. It consists of three 8-bit bidirectional I/O ports (24 I/O lines) which can be configured as per the requirement. Ports of 8255A 8255A has three ports, i.e., PORT A, PORT B, and PORT C. Port A contains one 8-bit output latch/buffer and one 8-bit input buffer. Port B is similar to PORT A. Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7-PC4) by the control word. These three ports are further divided into two groups, i.e. Group A includes PORT A and upper PORT C. Group B includes PORT B and lower PORT C. These two groups can be programmed in three different modes, i.e. the first mode is named as mode 0, the second mode is named as Mode 1 and the third mode is named as Mode 2. Features of 8255 A The prominent features
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